1. Field of the Invention
The present invention relates to the fabrication of a via hole, formed in several layers of insulator, and used to accommodate a laser repair procedure.
2. Description of Prior Art
Laser repairing, performed on high density memory chips, has allowed the yield of these high density memory chips, such as chips comprised with high density embedded, dynamic random access memory, (DRAM), to be increased. Laser repairing can be comprised of removing a defective DRAM array, while adding an additional non-defective, or a redundant array, to the DRAM chip. However to use laser repair, a feature such as a large via hole, opened in all the levels of insulator layer, and exposing the area, usually near or at the semiconductor surface, to be laser treated, has to be available. This can entail forming a via hole in all the levels of insulator layers, (referring to interlevel dielectric, (ILD), or inter-metal dielectric, (IMD), layers), which for an embedded DRAM array chip, can total an stack of insulator layers, about 5 to 10 micrometers in thickness. The ability to dry etch this thick stack of insulators, to create the via needed to accommodate laser repair, is difficult due to the large thickness of masking photoresist needed. A wet etching procedure, used to create the via, would result in isotropic undercutting, and possible yield loss. In addition, to optimize the repair procedure, a finite amount of insulator, between about 2000 to 8000 Angstroms, is needed to overlay the conductive fuse layer, that will be subjected to the laser repair procedure.
This invention will describe a novel procedure for fabricating a via hole, in the several levels of insulator, needed to accommodate the laser repair procedure. This invention will feature a polysilicon stop layer, formed on an underlying insulator layer, that is comprised with the optimum thickness, needed to allow laser repair of underlying arrays to occur. In addition, this invention will feature forming the large diameter via hole, in several levels of insulator layer, using the polysilicon stop layer, at the bottom of the large diameter via hole. The large diameter via hole, used for laser repair purposes, is simultaneously formed at each level of insulator layer, with the small diameter via holes, used to accommodate the conductive plugs, that are used between metal levels. The procedures, metal deposition and dry etching, used to create metal plugs in the small diameter via holes, result is metal spacers, on the sides of the large diameter via hole, thus protecting the interlevel insulators layers, from a wet etch procedure, used to remove portions of some of the interlevel insulator layers, that were not totally removed during the dry etching formation of the smaller via holes, with the final wet etch procedure used to expose the polysilicon stop layer. Prior art, such as Lippitt III, in U.S. Pat No. 5,235,205, describes the formation of a via hole, used for laser repair, but does not describe the novel metal spacers, used in this invention, used to protect the levels of insulator from a final wet etch procedure.